The Integrated Method
The integrated method uses a stepped time domain simulation of arc faults. Simulations are carried out in small successive time steps. For each time step, the calculations are made for bolted fault current at the faulted bus, the arc current at the fault, and the arc current through the protective devices. Incident energy is calculated for this time step and added to the incident energy accumulated up to the previous time step. Protective devices are evaluated for trip conditions. The memory variables for trip devices are integrated using the through current and information from the TCC. When a trip condition is found to exist at the end of the time step, the device is switched opened to interrupt the current. For relay controlled breakers, the breakers are opened with an additional delay equal to the rated opening time of the breakers after the relay has tripped. The simulation is run until the fault current reduces to zero. The arc flash boundary is calculated from the total accumulated energy.
The bolted fault currents are calculated using the ANSI/IEEE C37.010 standard. The momentary currents are used up to the first cycle. From 2-8 cycles, the interrupting time currents are used. Thereafter, the 30-cycle currents are used. This is a close approximation using the available standards and practices in short circuit calculations.
